Computer Architecture Tutorial

Meet CSE 203 - why hardware DNA matters for every software engineer, and how this InTelleX path is organized.

Set up your mental map of CSE 203 activities: Assembly Duel, Bottleneck Audit, Hardware Visualization, and Clock-Cycle Stress Test.

Compare the classic stored-program model with Harvard separation of instruction and data memory.

Walk the stack from problem statement through HLL, assembly, machine code, microarchitecture, and digital logic.

Master CPU time = Instruction Count × CPI × Clock Period - and what each term really means.

Calculate total cycles, effective CPI for mixed instruction mixes, and wall-clock execution time.

Design a lightweight profiler concept that tracks instruction mixes and graphs CPI for software blocks.

Define the ISA as the hardware/software interface: operations, registers, memory model, and encodings.

Contrast Reduced vs Complex Instruction Set designs and why modern machines borrow from both.

Learn register files, operand types, and the RISC-V / MIPS calling convention essentials.

Decode R-Type, I-Type, S-Type (and friends): fields, opcodes, and why formats stay regular.

Understand base+offset addressing, alignment, and how addressing modes affect hardware complexity.

Compile nested loops and conditionals by hand into clean assembly with minimal redundant instructions.

Manually trace register state and memory contents step-by-step - no emulator crutches.

Design a lightweight disassembler that maps binary machine words to human-readable assembly.

Represent unsigned and signed integers, two's complement, and overflow conditions.

Build intuition for full adders, subtract-via-negate, AND/OR/XOR, and shifts as ALU building blocks.

Design faster addition with generate/propagate signals - escape the ripple-carry bottleneck.

See how array multipliers and Wallace trees compress partial products for high-speed multiply.

Decode sign, exponent, mantissa; normalize; and handle corner cases that break naive intuition.

Specify a simulated ALU supporting arithmetic, logic, and shifts with clear control encodings.

Identify PC, instruction memory, register file, ALU, data memory, and the muxes that steer them.

Trace Fetch → Decode → Execute → Memory → Writeback for ALU, load, store, and branch instructions.

Compare hardwired combinational control with microprogrammed control stores and when each shines.

Model a single-cycle datapath that routes data correctly from opcode-driven control signals.

See how overlapping instruction stages multiplies throughput without magically shortening individual instruction latency.

Map IF, ID, EX, MEM, WB onto hardware resources and pipeline registers between stages.

Compute pipelined speedup, pipeline CPI with stalls, and the cost of unbalanced stages.

Manually plot multi-cycle execution charts and calculate speedup versus non-pipelined execution.

Specify a visualization that shows instructions propagating through a 5-stage pipeline in real time.

Consolidate adders, number systems, FP basics, and ALU control before the mid-term checkpoint.

Rehearse formats, addressing, and hand translation under timed conditions.

Trace control signals and mux settings for core instructions on a single-cycle blueprint.

Recognize resource conflicts when two stages need the same hardware in one cycle.

Classify read-after-write, write-after-read, and write-after-write dependencies in pipelines.

See why branches disrupt the pipeline and how delay slots or prediction respond.

Wire EX/MEM and MEM/WB results back to ALU inputs to slash many RAW stalls.

Insert NOPs / freeze pipeline registers safely when forwarding is not enough.

Compare predict-not-taken, static predictors, and 1-bit/2-bit dynamic predictors.

Analyze assembly for stalls and reschedule instructions to improve throughput.

Design a module that scans assembly, flags dependencies, and proposes forwarding paths.

Explain temporal and spatial locality - the reason caches and hierarchies work.

Map addresses to a single set: tag, index, offset - and compute hits/misses.

Compare associativity levels, replacement policies, and the hit-rate vs hardware cost trade-off.

Choose write policies and write-allocate vs no-write-allocate strategies with clear trade-offs.

Compute Average Memory Access Time from hit time, miss rate, and miss penalty - including multilevel caches.

Walk address streams through a small cache, counting hits/misses and tracking line updates.

Build an algorithmic cache simulator to sweep line size and associativity against AMAT.

Separate virtual from physical addresses and walk the role of page tables in translation.

Use Translation Lookaside Buffers to avoid walking page tables on every access.

Control devices by reading/writing reserved addresses - unify CPU access paths.

Compare busy-wait device service with interrupt-driven I/O and when each is appropriate.

Let devices transfer bulk data to memory without per-word CPU babysitting.

Build an automated transfer module that models DMA setup, bus grant, and completion interrupt.

Quantify the speedup ceiling when only part of a workload can be parallelized.

Classify SISD, SIMD, MISD, and MIMD - and map them to CPUs, GPUs, and clusters.

Differentiate data-level parallelism from thread-level parallelism in practical terms.

Track shared line states across cores so every reader sees a consistent memory story.

Simulate a multi-core environment tracking shared line state changes across processing cores.

Think jointly about ISA, compiler scheduling, and microarchitecture when chasing performance per watt.

Practice SIU engineering discipline: every design choice balances latency, area, and energy.

Tackle memory bus contention, synchronization overhead, and diminishing returns at scale.

Comprehensive drill on ISA encodings, hand translation, and single-cycle control before the final.

Drill hazard charts, forwarding, AMAT, and associativity questions for the comprehensive final.

Integrate ISA, datapath, pipeline, cache, and I/O into one coherent system narrative and portfolio packet.